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? e91845b67-te sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. ccd camera synchronization and timing signal generator cxd1254ar/aq absolute maximum ratings (ta=25 ?, v ss =0 v) supply voltage v ss ?.5 to +7.0 v input voltage v ss ?.5 to v dd +0.5 v output voltage v ss ?.5 to v dd +0.5 v operating temperature ?0 to +75 ? storage temperature ?5 to +150 ? recommended operating conditions supply voltage 4.75 to 5.25 v operating temperature ?0 to +75 ? description the cxd1254ar and CXD1254AQ ics generates the necessary synchronization and timing signals for camera systems employing ccd image sensors (icx044, icx045, icx046, etc.). features supports color (ntsc) and black & white (eia/ccir) systems on-chip electronic shutter on-chip horizontal (h) driver timing generator for mirror images applications ccd camera systems structure silicon gate cmos ic cxd1254ar CXD1254AQ 64 pin lqfp (plastic) 64 pin qfp (plastic)
? cxd1254ar/aq block diagram (pin no.s given for cxd1254ar) test generator reset generator 1/7 or 1/6 counter h-decoder 1/525 or 1/625 counter v-decoder v-control output control h-init v-relative counter v-rom (vd1) latch h-relative counter latch address counter h-rom (hd1) h-rom (hd2) h-rom (hd3) h-rom (rd1) h-rom (rd2) 48 49 54 58 52 1/65 counter 3 1 2 h-relative counter v-init latch latch latch latch address counter 62 63 64 6 4 5 reset ck generation 1/3 1/2 11 10 9 phase cont. serial- parallel converter gate shutter rom counter/gate select gate gate gate 16 13 12 14 15 27 29 26 31 21 23 33 34 35 36 18 20 37 38 19 25 39 45 46 28 30 test2 test3 ext test1 fld hd vd c kin osci osco cl ps ed0 ed1 ed2 enb d1 d2 d3 bf cblk sync 41 43 42 44 xdl1 xdl2 h1 h2 h3 h4 xshd xshp xsp1 xsp2 rg xsub pblk bfg id clp1 clp2 clp3 clp4 xv1 xv2 xv3 xv4 xsg1 xsg2
? cxd1254ar/aq pin configuration (1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 59 58 60 61 62 63 64 17 18 20 21 22 23 24 25 26 27 28 29 30 31 32 19 cxd1254ar fld htsg v dd ext v ss test2 nc v dd nc test3 v ss nc nc bf cblk sync v ss xv4 xsg2 xv3 xsg1 xv1 xv2 xsub v dd rg av ss h4 h3 h2 h1 av dd test1 v dd id pblk clp4 clp3 clp2 clp1 v ss bfg xdl2 xdl1 xsp2 xsp1 xshd xshp hd vd cl d1 d2 d3 trig v ss osci osco ckin enb ed0 ed1 ed2 ps mode d1 d2 d3 enb ed0 ed1 ed2 ps ext test2 pin no. 4 5 6 12 13 14 15 16 52 54 preset low low low high high high high high low low low high ntsc/eia ccir normal image mirror image color b/w normal shutter shutter speed serial input parallel input internal external normally low
? cxd1254ar/aq pin configuration (2) 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 59 58 60 61 62 63 64 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CXD1254AQ htsg v dd ext v ss test2 nc v dd nc test3 v ss nc nc bf xsg2 xv3 xsg1 xv1 xv2 xsub v dd rg av ss h4 h3 h2 h1 cblk sync hd vd cl d1 d2 d3 trig v ss osci osco ckin enb ed0 ed1 ed2 ps av dd fld test1 v dd id pblk clp4 clp3 clp2 clp1 v ss bfg xdl2 xdl1 xsp2 xsp1 xshd xshp v ss xv4 mode d1 d2 d3 enb ed0 ed1 ed2 ps ext test2 pin no. 6 7 8 14 15 16 17 18 54 56 preset low low low high high high high high low low low high ntsc/eia ccir normal image mirror image color b/w normal shutter shutter speed serial input parallel input internal external normally low
? cxd1254ar/aq pin description pin no. lqfp qfp 13 24 35 46 57 68 79 810 911 10 12 11 13 12 14 13 15 14 16 15 17 16 18 17 19 18 20 19 21 20 22 21 23 22 24 23 25 24 26 25 27 26 28 27 29 28 30 29 31 30 32 31 33 32 34 33 35 34 36 35 37 36 38 37 39 38 40 39 41 40 42 pin hd vd cl d1 d2 d3 trig v ss osci osco ckin enb ed0 ed1 ed2 ps av dd h1 h2 h3 h4 av ss rg v dd xsub xv2 xv1 xsg1 xv3 xsg2 xv4 v ss xshp xshd xsp1 xsp2 xdl1 xdl2 bfg v ss i/o o o o i i i i i o i i i i i i o o o o o o o o o o o o o o o o o o o o function horizontal drive pulse output vertical drive pulse output clock output ntsc/eia: 14.318 mhz ccir: 14.1875 mhz mode selection ?ow? ntsc/eia ?igh? ccir (pull-down resistor) mode selection ?ow? normal ?igh? mirror (pull-down resistor) mode selection ?ow? color ?igh? b/w (pull-down resistor) shutter speed setting pulse input (pull-up resistor) gnd for signal generator oscillator input ntsc/eia: 28.636 mhz ccir: 28.375 mhz oscillator output input for determining oscillator duty cycle shutter selection ?ow? normal ?igh? shutter (pull-up resistor) shutter speed control (pull-up resistor) shutter speed control (pull-up resistor) shutter speed control (pull-up resistor) shutter speed setting data format selection ?ow? serial ?igh? parallel (pull-up resistor) independent power supply for horizontal driver clock output for horizontal register driver clock output for horizontal register driver (leave open except for icx046.) clock output for horizontal register driver (use as h2 except for icx046.) clock output for horizontal register driver (leave open except for icx046.) independent gnd for horizontal driver reset gate pulse output power supply for timing generator sensor charge sweep output pulse output clock output for vertical register driver clock output for vertical register driver sensor charge readout pulse output clock output for vertical register driver sensor charge readout pulse output clock output for vertical register driver gnd for timing generator pre-charge level/sample-and-hold pulse output * 1 data sample-and-hold pulse output * 1 color separation sample-and-hold pulse output * 1 color separation sample-and-hold pulse output * 1 pulse output for delay line * 1 pulse output for delay line * 1 burst flag gate pulse output gnd for timing generator
? cxd1254ar/aq pin no. lqfp qfp 41 43 42 44 43 45 44 46 45 47 46 48 47 49 48 50 49 51 50 52 51 53 52 54 53 55 54 56 55 57 56 58 57 59 58 60 59 61 60 62 61 63 62 64 63 1 64 2 pin clp1 clp2 clp3 clp4 pblk id v dd test1 fld htsg v dd ext v ss test2 nc v dd nc test3 v ss nc nc bf cblk sync i/o o o o o o o i i/o i i i i o o o function pulse output for clamp pulse output for clamp pulse output for clamp pulse output for clamp blanking/cleaning pulse output line discrimination pulse output power supply for timing generator test input/h reset pulse input * 2 field pulse output/v reset pulse input * 2 xsg1, 2 controller/test input * 2 power supply for signal generator synchronization mode selection. ?ow? internal ?igh? external (pull-down resistor) gnd for signal generator test input (normally open) (pull-down resistor) used open power supply for signal generator used open test input (normally fixed at ?ow? gnd for signal generator used open used open burst flag pulse output composite blanking pulse output composite synchronization pulse output (note) * 1?utput determined by mode setting. * 2?unction determined by mode setting. outputs for pins determined by mode setting * 1 pin xshp xshd xsp1 xsp2 xdl1 xdl2 pin no. (lqfp) 33 34 35 36 37 38 xshp ( ) output xshd ( ) output xsp1 ( ) output xsp2 ( ) output xdl1 output xdl2 output o o o o o o o o o o o o shp ( ) output shd ( ) output (out put stopped) (out put stopped) (out put stopped) (out put stopped) d3 (pin 6) low (color) high (b/w)
? cxd1254ar/aq functions for pins determined by mode settings * 2 pin test1 fld htsg pin no. (lqfp) 48 49 50 test input (normally low) fld output xsg1, 2 control input (?ow?: off ?igh?: on) i o i i i i h reset pulse input v reset pulse input test input (normally low) ext (pin 11) low (internal) high (external) electrical characteristics 1) dc characteristics (v dd =5 v ?.25 v, topr= ?0 to +75 ?) item supply voltage input voltage output voltage 1 output voltage 2 cl, rg, xshp, xshd, xsp1, xsp2, xdl1, xdl2 output voltage 3 h1, h2, h3, h4 output voltage 4 osc0 feedback resistance pull-up resistor pull-down resistor symbol v dd v ih1 v il1 v oh1 v ol1 v oh2 v ol2 v oh3 v ol3 v oh4 v ol4 r fb r pu r pd conditions i oh =? ma i ol =4 ma i oh =? ma i ol =8 ma i oh =? ma i ol =8 ma i oh =? ma i ol =1 ma v in =v ss or v dd v il =0 v v ih =v dd min. 4.75 0.7 v dd v dd ?.5 v dd ?.5 v dd ?.5 v dd /2 500 k 40 k 40 k typ. 5.0 2 m 100 k 100 k max. 5.25 0.3 v dd 0.4 0.4 0.4 v dd /2 5 m 250 k 250 k unit v v v v v v v v v v v item input pin capacitance output pin capacitance input/output pin capacitance symbol c in c out c i/o min. typ. max. 9 11 11 unit pf pf pf 2) input/output capacitance (v dd =v i =0 v, f m =1 mhz)
? cxd1254ar/aq electronic shutter description pins for shutter ps, trig, enb inputs for overall mode setting xsub output ed0, ed1, ed2 inputs for shutter speed setting (note) regardless of shutter speed setting controlled by ps, ed0 to ed2, and trig, if enb is ?ow? the shutter will be off. the speed set by ps and ed0 to ed2 is subject to control by trig. mode description 1. trig (pull-up resistor) for normal shutter operation, trig should be either left open or set at high. for continuous variable shutter operation, input a clock pulse to trig. by taking out xsub pulses between downward pulses of xsg1 and trig, and thus stopping xsub pulses from the downward pulse of trig to the following downward pulse of xsg1, the shutter speed is determined. in order to increase the range of control when the trig pin is used to control the shutter speed, pins ed0 to ed2 (described in next section) must be pre-set to 1/10000 sec. (described in later section.) 2. ed0, ed1, and ed2 (shutter speed control) ps (selects between parallel/serial input) enb (shutter mode selection) 2-1. ps selects either parallel or serial input data format to be used for determining shutter speed. parallel input combination of the 3 bits, ed0, ed1, ed2, yields 8 possible shutter speed settings. serial input shutter speed is determined by inputting ed0 (strobe), and ed1 (clock), and ed2 (data) to respective pins. shutter speded vd hd xsgi trig xsub
? cxd1254ar/aq 2-1-1. [parallel input] (ps = h) ?for high speed shutter only table of shutter settings 2-1-2. [serial input] (ps = l) the combination of serial data smd1 and smd2 can be used to select one of four modes. shutter mode ?flickerless mode for eliminating flicker caused by oscillation frequency of fluorescent lights. ?high-speed shutter shutter speed faster than 1/60 sec. (ntsc/eia) or 1/50 sec. (ccir). ?low-speed shutter shutter speed slower than 1/60 sec. (ntsc/eia) or 1/50 sec. (ccir). ?no shutter shutter operation inactive. ed2 data is latched in the register on the rising edge of ed1 and the register contents are transferred during the low period of ed0. d1 x l h l h x x x x x x enb l h h h h h h h h h h ed0 x h h l l h l h l h l ed1 x h h h h l l h h l l ed2 x h h h h h h l l l l shutter speed shutter off 1/60 (s) 1/50 (s) 1/100 (s) 1/120 (s) 1/250 (s) 1/500 (s) 1/1000 (s) 1/2000 (s) 1/4000 (s) 1/10000 (s) mode smd1 smd2 flickerless low low high-speed shutter low high low-speed shutter high low no shutter high high ed1 (clk) ed2 (oata) edo (stb) d0 d1 d2 d3 d4 d5 d6 d7 d8 smd1 smd2 dummy
?0 cxd1254ar/aq ac characteristics t s2 t h2 t s1 t s0 t w0 ed2 ed1 ed0 symbol t s2 t h2 t s2 t w0 t s0 ed2 set-up time referenced from the ed1 rising edge ed2 hold-time referenced from the ed1 rising edge ed1 rise set-up time referenced from the ed0 rising edge ed0 pulse width ed0 rise set-up time referenced from the ed1 rising edge min. 20 ns 20 ns 20 ns 20 ns 20 ns max. 50 ? 2-1-3. [shutter speed calculation formula] high-speed shutter for ntsc/eia t= [262 10 ?(1ff 16 ?l 16 )] 63.56 + 34.78 ? ?l 16 : load value for ccir t= [312 10 ?(1ff 16 ?l16)] 64 + 35.6 ? ntsc/eia load value shutter speed calculated value 0fa 16 1/10000 1/10169 0fc 16 1/4000 1/4435 100 16 1/2000 1/2085 108 16 1/1000 1/1012 118 16 1/500 1/499 137 16 1/250 1/252 176 16 1/125 1/125 196 16 1/100 1/100 ccir load value shutter speed calculated value 0c8 16 1/10000 1/10040 0ca 16 1/4000 1/4349 0ce 16 1/2000 1/2068 0d6 16 1/1000 1/1004 0e6 16 1/500 1/495 105 16 1/250 1/250 143 16 1/125 1/125 149 16 1/100 1/120 low-speed shutter n = 2 (1ff 16 ?l 16 ) fld ?ff?cannot be used as a load value. load value 1fe 16 1fd 16 : 101 16 100 16 shutter speed (fld) 2 4 : 508 510
?1 cxd1254ar/aq external synchronization mode description h reset the reset process is started from the first falling edge of the inputted reset pulse. the next reset occurs only when there is a divergence of at least a clock cycles (0.98 ?) from the edge. the minimum reset pulse width is 0.98 ?. the hd output reset position leads the h reset input by 2.45 to 2.94 ?. v reset the vd output reset position leads the falling edge of the v reset input by 3.5 to 4.0 h for ntsc/eia and by 3.0 to 3.5 h for pal. the minimum reset pulse width is 32 ?. 1h 0.98s and over 2.45 to 2.94s hd pulse reset at the falling edge of 0.98s and over h reset input hd output 1v 32s and over v reset input vd output 9h 3.5 to 4.0h (ntsc/eia) 3.0 to 3.5h (ccir)
?2 cxd1254ar/aq timing chart (1) odd field for eia (black & white), the tg system output follows the vd switching point by 1h. (for both odd and even.) blk fld vd hd sync bf xsg1 xsg2 xv1 xv2 xv3 xv4 pblk clp1 clp2 clp3 clp4 id bfg
?3 cxd1254ar/aq even field blk fld vd hd sync bf xsg1 xsg2 xv1 xv2 xv3 xv4 pblk clp1 clp2 clp3 clp4 id bfg
?4 cxd1254ar/aq timing chart (2) odd field fld blk vd sync bf (4?) bf (2?) xsg1 xsg2 xv1 xv2 xv3 xv4 pblk clp1 clp2 clp3 clp4 id bfg hd
?5 cxd1254ar/aq even field fld blk vd sync bf (3?) bf (1?) xsg1 xsg2 xv1 xv2 xv3 xv4 pblk clp1 clp2 clp3 clp4 id bfg hd
?6 cxd1254ar/aq ntsc/eia normal mode h direction timing chart timing chart (3) hd hsync bf blk eq vsync cl clk h1 h2 h3 h4 rg xshp xshd shp shd xsp1 xsp2 xdl1 xdl2 xv1 xv2 xv3 xv4 pblk clp1 clp2 clp3 clp4 id bfc xsub b/w color
?7 cxd1254ar/aq ntsc/eia mirror mode h direction timing chart timing chart (4) hd blk hsync eq vsync bf cl clk h1 h2 h3 h4 rg xshp xshd shp shd xsp1 xsp2 xdl1 xdl2 xv1 xv2 xv3 xv4 pblk clp1 clp2 clp3 clp4 id bfc xsub b/w color
?8 cxd1254ar/aq ccir normal mode h direction timing chart timing chart (5) hd blk hsync eq vsync bf cl clk h1 h2 h3 h4 rg xshp xshd shp shd xsp1 xsp2 xdl1 xdl2 xv1 xv2 xv3 xv4 pblk clp1 clp2 clp3 clp4 id bfc xsub
?9 cxd1254ar/aq ccir mirror mode h direction timing chart timing chart (6) hd blk hsync eq vsync bf cl clk h1 h2 h3 h4 rg xshp xshd shp shd xsp1 xsp2 xdl1 xdl2 xv1 xv2 xv3 xv4 pblk clp1 clp2 clp3 clp4 id bfc xsub
?0 cxd1254ar/aq application circuit (lqfp package) cxd1254ar 49 50 51 52 53 54 55 56 57 59 58 60 61 62 63 64 17 18 20 21 22 23 24 25 26 27 28 29 30 31 32 19 driver ccd imase sensor 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 signal processing shutter control 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 osc ntsc/eia : 28.6363mhz ccir : 28.375mhz ?please use a clock crystal which operates on a fundamental wave. application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
cxd1254ar/aq ?1 sony code eiaj code jedec code package material lead treatment lead material package weight epoxy / phenol resin plating 42/copper alloy package structure 12.0 0.2 * 10.0 0.1 (0.22) 0.18 ?0.03 + 0.08 0.5 0.08 1 16 17 32 33 48 49 64 0.5 0.2 (11.0) 0.127 ?0.02 + 0.05 a 1.5 ?0.1 + 0.2 0.1 0.1 0.5 0.2 0?to 10 64pin lqfp (plastic) lqfp-64p-l01 qfp064-p-1010 0.3g detail a 0.1 solder/palladium note: * ?dimensions do not include mold protrusion. sony code eiaj code jedec code 23.9??.4 20.0?.1 1.0 0.4 ?0.1 + 0.15 14.00.1 1 19 20 32 33 51 52 64 0.15 ?0.05 + 0.1 2.75 ?0.15 16.3 0.1 ?0.05 + 0.2 0.8 0.2 m 0.12 0.15 +?.4 17.9??.4 +0.4 + 0.35 64pin qfp(plastic) qfp?4p?01 * qfp064??420 package material lead treatment lead material package weight epoxy resin solder/palladium copper /42 alloy package structure plating 1.5g package outline unit : mm cxd1254ar CXD1254AQ

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